Semiconductors devices are becoming more highly-integrated and are operating at increasingly higher clock speeds, thereby resulting in higher-performance electronic systems being produced. The above-mentioned higher-performance electronic systems include, for example, portable multimedia players, personal computers or electronic communication devices. Accordingly, manufacturers of integrated circuit chips are seeking to manufacture chip internal circuits according to a reduced critical dimension.
However, static electricity may significantly damage electronic devices, including integrated-circuit chips. As a result, to protect internal circuits from static electricity, protection devices are typically being employed within input or output paths of integrated circuit chips, and various kinds of integrated circuits are being tested through an ESD (Electrostatic Discharge) test before shipment.
For example, U.S. Pat. No. 5,514,892, describes an electrostatic discharge protection device having diodes that are provided in a lower part of a wire bond pad.
Manufacturers have been employing a suicide process using a low electric resistance for producing semiconductor integrated circuits, to obtain higher performance semiconductor devices. However, the above silicide process may result in certain difficulties with regard to electrostatic discharge protection such as, the capacity of parasitic diodes within a chip may be small when using this process. For example, the parasitic diodes may be herein parasitically formed between a source/drain connected to an input/output terminal such as a metal-oxide semiconductor field-effect transistor (MOSFET) and a substrate on which the source/drain are formed or a well. Moreover, the protection diodes have substantially more load from static electricity, and thus the pressure resistance characteristic may be relatively prominent within a limited occupying area. In other words, it may be relatively more difficult to protect the ESD in a semiconductor integrated circuit formed by a silicide process, and thus chip designers have been trying to obtain an improved ESD protection level.
For example, in employing the ESD protection device shown in FIG. 1 within a chip, chip designers have performed various analyses for an ESD failure mechanism using test modes such as shown in FIG. 2 to provide for a situation in which the ESD protection may fail to execute the test for chips.
FIG. 1 illustrates wired protection devices applied to a pad in a conventional semiconductor integrated circuit. FIG. 2 illustrates various electrostatic discharge stress modes in a conventional semiconductor integrated circuit.
In FIG. 2, four modes, a PS (Pin to VSS Positive) mode, an NS (Pin to VSS Negative) mode, a PD (Pin to VDD Positive) mode and an ND (Pin to VDD Negative) mode, indicate the modeling of stress from static electricity. The four modes belong to stresses related to HBM (Human Body Model) or MM (Machine Model), and to a CDM (Changed Device Model). In the PS mode and the PD mode, positive static is input to pins of a chip, and in the NS mode and the ND mode, negative static is input to pins of a chip.
Referring to FIG. 1, an integrated circuit includes an internal circuit 8 connected between a power supply voltage VDD and a ground voltage VSS. In the integrated circuit shown in FIG. 1, a pad 2 such as, for example, a bonding pad is connected to electrostatic discharge protection diodes 4 and 6 through a connection point NO1. Moreover, in FIG. 1, a clamp circuit 7 to limit voltage may be connected between the power supply voltage VDD and the ground voltage VSS, and the pad 2 may be installed corresponding to pins such as, for example, an input pin, output pin or input/output pin.
A p-type diode 4 is an electrostatic discharge protection diode to discharge static electricity to a power supply voltage (VDD) line when a positive static flows to the pad 2 from the power supply voltage VDD. An n-type diode 6 is an electrostatic discharge protection diode to discharge static electricity to a ground voltage (VSS) line when a negative static flows to the pad 2 from the ground voltage VSS. As shown in FIG. 1, when an electrostatic voltage flows to each diode 4, 6 with a level over a turn-on voltage level, each diode 4, 5 is turned on. Thus, current based on an electrostatic voltage is discharged to the power supply voltage VDD and the ground voltage VSS through respective diodes 4 and 6 without flowing into the internal circuit 8, and so the internal circuit of the integrated circuit chip can be protected from static electricity.
The protection diodes of FIG. 1 may be disposed under the pad 2 as shown in FIG. 3 to reduce chip size. FIG. 3 is a schematic sectional view illustrating an example in which a protection device of FIG. 1 is formed on a substrate.
Referring to FIG. 3, on a substrate 50, an n-type well 60 where n-type ions exist, and a p-type well 70 where p-type ions exist, are formed. High-density diffusion regions 62, 64 and 65 formed in the n-type well 60 constitute the p-type diode 4 of FIG. 1, and high-density diffusion regions 72, 74 and 75 of the p-type well 70 constitute the n-type diode 6 of FIG. 1. From among the diffusion regions, regions 62,74 and 75 are the regions diffused after a high density implantation of p-type ions, and regions 72,64 and 65 are the regions diffused after a high density implantation of n-type ions. The diffusion regions 62 and 72 are connected to the connection point NO1 through respective connected lines CP1 and CP2, and the connection point NO1 is electrically connected to a lower port of the pad 2. The regions 64 and 75 are connected, respectively to a line 1 of power supply voltage VDD and a line 3 of ground voltage VSS. The region 65 seems to be distanced from the region 64 by a sectional structure in the drawing, but the regions 65 and 64 are substantially the same diffused region. Likewise, the region 74 is the same diffused region as the region 75.
In forming the ESD protection diodes shown in FIG. 1 on the substrate, layout dependency is significant. Therefore, it may be desirable to form them under the pad 2 as shown in the sectional structure of FIG. 3. However, the pad 2 has a bonding region BA wire-bonded to electrically connect to a corresponding pin, and so a bonding force is applied to lower layers. Thus, careful consideration in forming an electrical contact structure is required.
In the conventional art, ESD protection devices are formed under respective pads to reduce chip size. Nevertheless, with the above-mentioned conventional semiconductor devices, a weakened portion for pressure resistance in a connected part between a pad and a protection device is also generated, which in turn may lead to an electrostatic breakdown in the semiconductor device.
Thus, there is a need for a semiconductor device capable of improving electrostatic discharge protection without increasing the size of the device and which also provides an improved pressure resistance characteristic against static electricity.